From 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 22 Jul 2023 12:49:05 -0400 Subject: mb/*: Update SPD mapping for sandybridge boards Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) Reviewed-by: Martin L Roth --- src/mainboard/lenovo/t530/variants/t530/overridetree.cb | 1 + src/mainboard/lenovo/t530/variants/t530/romstage.c | 7 ------- src/mainboard/lenovo/t530/variants/w530/overridetree.cb | 1 + src/mainboard/lenovo/t530/variants/w530/romstage.c | 9 --------- 4 files changed, 2 insertions(+), 16 deletions(-) (limited to 'src/mainboard/lenovo/t530') diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb index 78f7b9b34c..98551ac968 100644 --- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH device pci 1f.0 on # PCI-LPC bridge diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c index 22bf0764aa..2290bcea13 100644 --- a/src/mainboard/lenovo/t530/variants/t530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c @@ -1,14 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb index 115bc1f12a..77b75fd237 100644 --- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" device domain 0 on device pci 02.0 on # Internal graphics VGA controller subsystemid 0x17aa 0x21f5 diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c index f3ccc14266..7458d1ad4d 100644 --- a/src/mainboard/lenovo/t530/variants/w530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c @@ -1,16 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[3], 0x53, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ -- cgit v1.2.3