From f1b58b78351d7ed220673e688a2f7bc9e96da4e2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 1 Mar 2019 13:43:02 +0200
Subject: device/pci: Fix PCI accessor headers
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/lenovo/t430s/romstage.c                | 1 +
 src/mainboard/lenovo/t430s/smihandler.c              | 1 +
 src/mainboard/lenovo/t430s/variants/t430s/romstage.c | 1 +
 3 files changed, 3 insertions(+)

(limited to 'src/mainboard/lenovo/t430s')

diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index ab2bb0a442..4edd5c6131 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c
index d69f6b6f7c..876d81c0d7 100644
--- a/src/mainboard/lenovo/t430s/smihandler.c
+++ b/src/mainboard/lenovo/t430s/smihandler.c
@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <ec/acpi/ec.h>
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
index 1b1c4b2b79..33d65dd5ab 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
@@ -18,6 +18,7 @@
 #include <option.h>
 #include <arch/byteorder.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-- 
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