From c36b5ea18983e3dbb021ae3012698d1357dcdf66 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 5 Feb 2024 16:11:26 -0500 Subject: mb/*: Copy bd82x6x boards' USB port config into devicetree For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t420s/devicetree.cb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/mainboard/lenovo/t420s') diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 4ce90772a5..b358885069 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -60,6 +60,23 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {0, 1, -1}, /* P0: empty */ + {1, 1, 1}, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */ + {1, 0, -1}, /* P3: WWAN, no OC */ + {1, 1, -1}, /* P4: smartcard, no OC */ + {1, 1, -1}, /* P5: ExpressCard, no OC */ + {0, 0, -1}, /* P6: empty */ + {0, 0, -1}, /* P7: empty */ + {0, 1, -1}, /* P8: empty (touch panel) */ + {1, 0, 5}, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + {1, 0, -1}, /* P10: fingerprint reader, no OC */ + {1, 1, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: docking, no OC */ + {1, 1, -1} /* P13: camera (LCD), no OC */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R -- cgit v1.2.3