From 9c538348d8ccaef2c3dd6b898a1f44b00ea59690 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 16:42:33 +0100 Subject: nb/intel/sandybridge: Make the mainboard_rcba_config hook optional This also changes the name to mainboard_late_rcba_config to better reflect what it does. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/lenovo/t420s/romstage.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/lenovo/t420s') diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 72cbcad245..7b97ff7e75 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -54,10 +54,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 1, -1 }, /* P0 empty */ { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ -- cgit v1.2.3