From 89b8c238306e18792433717053649b61b91f57e6 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 00:58:15 +0100 Subject: mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16 This bit is used to indicate xHCI routing across reboots. If anything, coreboot should act on it, not set it during boot. ASL code would be supposed to set it. Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/t420s/early_init.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/mainboard/lenovo/t420s/early_init.c') diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 1357a0ae52..e2cdebfe35 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -49,11 +49,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 1, -1 }, /* P0 empty */ { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ -- cgit v1.2.3