From 7e577ad22f2f7fb6e2fca062f87c93e1c1dc3344 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 15:14:07 +0200 Subject: AGESA f14/f15tn/f16kb: Factor out memory settings We use the same values everywhere, so we might as well factor them out. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Krystian Hebel --- src/mainboard/lenovo/g505s/buildOpts.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/mainboard/lenovo/g505s/buildOpts.c') diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index f4993d6450..fd1c977da4 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -346,16 +346,5 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { }; #define BLDCFG_FCH_SCI_MAP_LIST (&lenovo_g505s_sci_map[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* AGESA nonsense: this header depends on the definitions above */ #include -- cgit v1.2.3