From 657d68bddc030e38bc19eb4eef07f59b5e5258e4 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 3 Dec 2019 12:36:09 +0200 Subject: AGESA,binaryPI: Move PORT80 selection to C bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/lenovo/g505s/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/lenovo/g505s/Kconfig') diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 815c7d5734..b220b97b06 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_MP_TABLE -- cgit v1.2.3