From 07921540dda79d810d8bfc6be211513c238a0d63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 17:22:00 +0300 Subject: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15227 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/lanner/em8510/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/lanner') diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 0a8c4d7cb5..2e5a125fb9 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -31,6 +31,7 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) @@ -42,8 +43,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) { #if 0 -- cgit v1.2.3