From 6c83a71b0a803c922b02b613e927d4c49b944c32 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 00:25:18 +0200 Subject: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Marvin Evers Reviewed-by: Erik van den Bogaert Reviewed-by: Michael Niewöhner Reviewed-by: Jonathon Hall --- .../kontron/bsl6/variants/bsl6/overridetree.cb | 25 +++++++++++++--------- 1 file changed, 15 insertions(+), 10 deletions(-) (limited to 'src/mainboard/kontron') diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index ecfcd6f66a..6657fa9f29 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -8,19 +8,24 @@ chip soc/intel/skylake register "PcieRpEnable[ 3]" = "1" register "PcieRpEnable[11]" = "1" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)" - register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" - register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" - register "SataPortsEnable[3]" = "1" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [5] = USB2_PORT_LONG(OC2), + [6] = USB2_PORT_LONG(OC3), + [7] = USB2_PORT_LONG(OC3), + [8] = USB2_PORT_MID(OC4), + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), + [1] = USB3_PORT_DEFAULT(OC0), + [2] = USB3_PORT_DEFAULT(OC1), + [3] = USB3_PORT_DEFAULT(OC1), + }" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end -- cgit v1.2.3