From e61dd0f7a2be83ce5ba87d74f7384111576ffd49 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 6 May 2014 23:53:09 +1000 Subject: southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5669 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'src/mainboard/jetway') diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 8c05236515..bfd24cb60c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -44,10 +44,6 @@ #include #include -/* FIXME: should not include .c files */ -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" - /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) @@ -188,14 +184,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif /* CONFIG_HAVE_ACPI_RESUME */ - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); -- cgit v1.2.3