From b3ae1867d1a4b495a56078f521bebec9981f7494 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 18 Apr 2011 23:51:12 +0000 Subject: * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/jetway/pa78vm5/romstage.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/mainboard/jetway') diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 05b0e8b40a..3fd3972559 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -112,13 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); -- cgit v1.2.3