From 86f4ca5b4b99a799b403e61a90aa24d103fb7f2f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 13 Mar 2015 13:27:58 -0500 Subject: cpu/amd/model_10xxx: Add support for early cbmem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/8489 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Tested-by: Raptor Engineering Automated Test Stand --- src/mainboard/jetway/pa78vm5/romstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/jetway') diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398dde..df30a690eb 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* -- cgit v1.2.3