From 63f28c00aa32662c432565fc417e1f9d1fde6122 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Sat, 26 Apr 2014 15:21:45 +1000 Subject: superio/fintek/f71869ad: Make hwm devicetree configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provision the configuration of the Fintek F71869AD Hardware Monitor's configuration by way of devicetree.cb. Make use of this in the jetway/nf81-t56n-lf board to properly control fan's. Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5580 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/mainboard/jetway') diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 1c8853dd21..75184d4211 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -61,6 +61,18 @@ chip northbridge/amd/agesa/family14/root_complex register "multi_function_register_3" = "0x24" register "multi_function_register_4" = "0x00" register "multi_function_register_5" = "0x60" +# HWM configuration registers + register "hwm_smbus_address" = "0x98" + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_temp_map_sel" = "0x8c" +# # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, -- cgit v1.2.3