From 3d5e1e5d52b83306bcc8a32fc26f89d7f25bbb09 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Tue, 3 Dec 2019 14:06:02 +0200
Subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

With LPC decode enables explicitly set in C env bootblock,
this call can be delayed to happen before AMD_INIT_RESET.

Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/jetway/nf81-t56n-lf/romstage.c')

diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index a971c15d52..5e61bddfcc 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -17,11 +17,13 @@
 #include <northbridge/amd/agesa/state_machine.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71869ad/f71869ad.h>
+#include <sb_cimx.h>
 
 /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
 #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
+	sb_Poweron_Init();
 	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 }
-- 
cgit v1.2.3