From c896df7f158cf759906f4f164330fb552bbe0fec Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:16:01 +0000 Subject: mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/jetway/nf81-t56n-lf/bootblock.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/mainboard/jetway/nf81-t56n-lf/bootblock.c (limited to 'src/mainboard/jetway/nf81-t56n-lf/bootblock.c') diff --git a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c new file mode 100644 index 0000000000..5ecfaf74f8 --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ +#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) + +void bootblock_mainboard_early_init(void) +{ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} -- cgit v1.2.3