From 356b519049e6d40e15b2e4a85cae654e2e8df8ba Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 21:53:37 -0600 Subject: mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references Change-Id: I1f906c8c465108017bc4d08534653233078ef32d Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20343 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/iwill/dk8_htx/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/romstage.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/iwill') diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index b1fcdd1577..74770d4dc5 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -4,7 +4,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include #endif #include diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 9d29ae27f3..47d2619048 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -112,7 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); -- cgit v1.2.3