From f7116c3bd08e27fba8f1fb1ea25cfb8c4b592c67 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Fri, 3 Apr 2009 16:29:35 +0000 Subject: There are more than a dozen targets in the v2 tree which refer to ROMCC in their Config.lb but never use it. There's no point in keeping dead code around. This patch removes ROMCC remainders from Config.lb and kills orphaned auto.c and failover.c in the affected mainboard directories. arima/hdama ibm/e325 ibm/e326 iwill/dk8s2 iwill/dk8x msi/ms9282 newisys/khepri sunw/ultra40 tyan/s2891 tyan/s2892 tyan/s2895 tyan/s4880 tyan/s4882 Abuild log is completely identical with and without the patch. With this patch, the last ROMCC remainders for K8 boards are gone. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/iwill/dk8x/Config.lb | 56 ----------- src/mainboard/iwill/dk8x/auto.c | 189 ------------------------------------ src/mainboard/iwill/dk8x/failover.c | 66 ------------- 3 files changed, 311 deletions(-) (limited to 'src/mainboard/iwill/dk8x') diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb index 91fd3fbe3e..938ae2ca8d 100644 --- a/src/mainboard/iwill/dk8x/Config.lb +++ b/src/mainboard/iwill/dk8x/Config.lb @@ -47,8 +47,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./auto.o @@ -65,30 +63,6 @@ makerule ./auto.inc action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end -else -## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - end ## @@ -101,7 +75,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -109,7 +82,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -122,24 +94,16 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -147,12 +111,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE -if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds -else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end end ### @@ -162,27 +121,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit cpu/x86/sse/enable_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse/disable_sse.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/iwill/dk8x/auto.c b/src/mainboard/iwill/dk8x/auto.c index 2d4d6f4d15..e69de29bb2 100644 --- a/src/mainboard/iwill/dk8x/auto.c +++ b/src/mainboard/iwill/dk8x/auto.c @@ -1,189 +0,0 @@ -#define ASSEMBLY 1 -#include -#include -#include -#include -#include -#include -#include -#include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include - -#include "superio/nsc/pc87360/pc87360_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) - -static void hard_reset(void) -{ - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); -} - -/* - * GPIO28 of 8111 will control H0_MEMRESET_L - * GPIO29 of 8111 will control H1_MEMRESET_L - */ -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); - } - else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); - } -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); - udelay(90); - } -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/amdk8/raminit.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "sdram/generic_sdram.c" -#include "northbridge/amd/amdk8/resourcemap.c" -#include "cpu/amd/dualcore/dualcore.c" - -#define FIRST_CPU 1 -#define SECOND_CPU 1 -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) -static void main(unsigned long bist) -{ - static const struct mem_controller cpu[] = { -#if FIRST_CPU - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, -#endif -#if SECOND_CPU - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, -#endif - }; - - int needs_reset; - unsigned nodeid; - - if (bist == 0) { - k8_init_and_stop_secondaries(); - } - /* Setup the console */ - pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - setup_default_resource_map(); - needs_reset = setup_coherent_ht_domain(); - needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - -#if 0 - print_pci_devices(); -#endif - enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif - - memreset_setup(); - sdram_initialize(ARRAY_SIZE(cpu), cpu); - -#if 1 - dump_pci_devices(); -#endif -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 2)); -#endif - - /* Check all of memory */ -#if 0 - msr_t msr; - msr = rdmsr(TOP_MEM); - print_debug("TOP_MEM: "); - print_debug_hex32(msr.hi); - print_debug_hex32(msr.lo); - print_debug("\r\n"); -#endif -#if 0 - ram_check(0x00000000, msr.lo); -#endif -#if 0 - static const struct { - unsigned long lo, hi; - } check_addrs[] = { - /* Check 16MB of memory @ 0*/ - { 0x00000000, 0x01000000 }, -#if TOTAL_CPUS > 1 - /* Check 16MB of memory @ 2GB */ - { 0x80000000, 0x81000000 }, -#endif - }; - int i; - for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { - ram_check(check_addrs[i].lo, check_addrs[i].hi); - } -#endif -} diff --git a/src/mainboard/iwill/dk8x/failover.c b/src/mainboard/iwill/dk8x/failover.c index 262fdd60bd..e69de29bb2 100644 --- a/src/mainboard/iwill/dk8x/failover.c +++ b/src/mainboard/iwill/dk8x/failover.c @@ -1,66 +0,0 @@ -#define ASSEMBLY 1 -#include -#include -#include -#include -#include -#include -#include "pc80/mc146818rtc_early.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" -#include "northbridge/amd/amdk8/early_ht.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "northbridge/amd/amdk8/reset_test.c" - -static unsigned long main(unsigned long bist) -{ - unsigned nodeid; - - /* Make cerain my local apic is useable */ - enable_lapic(); - - /* Is this a cpu only reset? */ - if (early_mtrr_init_detected()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the 8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} -- cgit v1.2.3