From 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 20 Nov 2010 10:31:00 +0000 Subject: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/iwill/dk8s2/romstage.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'src/mainboard/iwill/dk8s2/romstage.c') diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index b15643adaa..2d4efe27a1 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +#include #include "cpu/amd/car/post_cache_as_ram.c" -- cgit v1.2.3