From a0aff6e15988f918b926c4cd222537d2f5a3f878 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Fri, 26 Apr 2024 17:35:05 +0800
Subject: soc/intel/xeon_sp: Add get_cxl_mode

Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.

Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.

TEST=Build and boot on intel/archercity CRB with no significant log
differences

Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/inventec/transformers/Makefile.mk |  2 ++
 src/mainboard/inventec/transformers/util.c      | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 src/mainboard/inventec/transformers/util.c

(limited to 'src/mainboard/inventec')

diff --git a/src/mainboard/inventec/transformers/Makefile.mk b/src/mainboard/inventec/transformers/Makefile.mk
index ecb6ef2217..eb859d3d69 100644
--- a/src/mainboard/inventec/transformers/Makefile.mk
+++ b/src/mainboard/inventec/transformers/Makefile.mk
@@ -2,5 +2,7 @@
 
 bootblock-y += bootblock.c
 romstage-y += romstage.c
+romstage-y += util.c
 romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c
+ramstage-y += util.c
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/inventec/transformers/util.c b/src/mainboard/inventec/transformers/util.c
new file mode 100644
index 0000000000..5197b23292
--- /dev/null
+++ b/src/mainboard/inventec/transformers/util.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/ocp/include/vpd.h>
+#include <soc/chip_common.h>
+#include <soc/util.h>
+
+#if CONFIG(SOC_INTEL_HAS_CXL)
+enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	int ocp_cxl_mode = get_cxl_mode_from_vpd();
+	switch (ocp_cxl_mode) {
+	case CXL_SYSTEM_MEMORY:
+		return XEONSP_CXL_SYS_MEM;
+	case CXL_SPM:
+		return XEONSP_CXL_SP_MEM;
+	default:
+		return XEONSP_CXL_DISABLED;
+	}
+}
+#endif
-- 
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