From f4fa906270623125316f1203766d693adda43739 Mon Sep 17 00:00:00 2001
From: Anil Kumar <anil.kumar.k@intel.com>
Date: Thu, 30 Jul 2020 14:31:00 -0700
Subject: mb/tglrvp: Update SPD files for Hynix

- Increase DDR Frquency limit to support data rate 4266 Mbps

Bug=None
Test=Build and boot on tglrvp hardware;
     $dmidecode --type 17 reflects memory Speed = 4266

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44149
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mainboard/intel')

diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
index 2ff9ed382e..4bf724e827 100644
--- a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
+++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
@@ -1,5 +1,5 @@
 23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00
-00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60
+00 00 04 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-- 
cgit v1.2.3