From cf32fd172928467ac5bbd4fb372b71230c81cf12 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 19 Dec 2018 18:02:17 +0530 Subject: soc/intel/common: Remove common chip config use_fsp_mp_init This patch ensures to make use of common MP Init Kconfig to choose desire method to peform MP initialization for platform. Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/intel/saddlebrook/Kconfig | 1 + src/mainboard/intel/saddlebrook/devicetree.cb | 5 ----- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 524bcca011..f2b7344aaa 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS select SADDLEBROOK_USES_FSP1_1 select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION + select USE_INTEL_FSP_MP_INIT config SADDLEBROOK_USES_FSP1_1 bool "FSP driver 1.1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 8f78249b3b..2f84a5dde5 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,11 +140,6 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - # Skip coreboot MP Init - register "common_soc_config" = "{ - .use_fsp_mp_init = 1, - }" - # Enable x1 slot register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" -- cgit v1.2.3