From bcfcfa4473357eb6272bc8bcc5e03f4ba517bcd2 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 3 Jun 2013 10:41:12 -0700 Subject: haswell: Update pei_data to match ref code - Add a new USB location field - Add a new "ddr_refresh_2x" field, enabled on Falco only - Fix copy+paste bug in baskingridge Checked that tREFI is halved during memory setup in the memory training log: tREFImin = 6240 << DEFAULT C(0).tREFI = 0xc30 << MODIFIED (=3120) C(0).tREFI = 0xc30 << MODIFIED (=3120) Also ensure that the SD card is detected properly again. Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/57349 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4219 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/mainboard/intel/baskingridge/romstage.c | 44 +++++++++++++++++++---------- src/mainboard/intel/wtm2/romstage.c | 24 ++++++++++------ 2 files changed, 45 insertions(+), 23 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1dc49603a9..ee516d9886 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -95,21 +95,35 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel1_disabled: 0, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */ - { 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */ - { 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */ - { 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */ - { 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */ - { 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */ - { 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */ - { 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */ - { 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */ - { 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */ - { 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */ - { 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ + USB_PORT_DOCK }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 0a24e48ba4..c4cce2e2c1 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -101,14 +101,22 @@ void mainboard_romstage_entry(unsigned long bist) max_ddr3_freq: 1600, usb2_ports: { /* Length, Enable, OCn# */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P0: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P1: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P2: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P3: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P4: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P5: */ - { 0x40, 1, USB_OC_PIN_SKIP }, /* P6: */ - { 0x40, 0, USB_OC_PIN_SKIP }, /* P7: Disable SDCARD due to hang */ + { 0x40, 1, USB_OC_PIN_SKIP, /* P0: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P1: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P2: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P3: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P4: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P5: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P6: */ + USB_PORT_FRONT_PANEL }, + { 0x40, 1, USB_OC_PIN_SKIP, /* P7: */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ -- cgit v1.2.3