From b5df65a9aaee50421913ace6d7a4b35e0ddff676 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 12 Nov 2022 14:51:49 +0100 Subject: mb/*: Replace SNB PCI devices with references from chipset.cb Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Elyes Haouas --- src/mainboard/intel/dcp847ske/devicetree.cb | 52 +++++++++++++------------- src/mainboard/intel/emeraldlake2/devicetree.cb | 48 ++++++++++++------------ 2 files changed, 50 insertions(+), 50 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 5400af773d..885043649c 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -12,9 +12,9 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0x06" device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref host_bridge on end # Host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "sata_port_map" = "0x1" @@ -23,25 +23,25 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff - device pci 14.0 off end # USB xHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 off end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1c.0 on end # PCIe Port #1 (unused) - device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA) - device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref xhci off end # USB xHCI + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 off end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref pcie_rp1 on end # PCIe Port #1 (unused) + device ref pcie_rp2 on end # PCIe Port #2 (full-length mPCIe/mSATA) + device ref pcie_rp3 on end # PCIe Port #3 (half-length mPCIe) + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 4e.0 off end # Floppy device pnp 4e.1 off end # Parallel port @@ -82,10 +82,10 @@ chip northbridge/intel/sandybridge device pnp 4e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 2eeb745014..ea17cc8cce 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -20,8 +20,8 @@ chip northbridge/intel/sandybridge end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -41,28 +41,28 @@ chip northbridge/intel/sandybridge # SuperIO range is 0x700-0x73f register "gen3_dec" = "0x003c0701" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (Debug) - device pci 1c.3 on end # PCIe Port #4 (LAN) - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 (WLAN) + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 (Debug) + device ref pcie_rp4 on end # PCIe Port #4 (LAN) + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end -- cgit v1.2.3