From b4f47e8067a7ef55ad5e2f18058031a871edbfef Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 11 Nov 2023 17:25:48 -0500 Subject: nb/intel/haswell: Move SPD addresses to devicetree Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy. Patch also covers recently added Z97 boards using Broadwell MRC. Also update util/autoport to match. abuild passes for all affected boards. autoport builds, but otherwise untested. Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/baskingridge/devicetree.cb | 1 + src/mainboard/intel/baskingridge/romstage.c | 9 --------- 2 files changed, 1 insertion(+), 9 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 3226170008..cd2c84ee06 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -11,6 +11,7 @@ chip northbridge/intel/haswell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 936703bce7..0963eb801e 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void mainboard_config_rcba(void) @@ -40,14 +39,6 @@ void mainboard_config_rcba(void) RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ -- cgit v1.2.3