From b4e275f97bc5221b98b91bb5b54f088d07570a57 Mon Sep 17 00:00:00 2001
From: Vaibhav Shankar <vaibhav.shankar@intel.com>
Date: Wed, 11 Oct 2017 17:37:53 -0700
Subject: mainboard/intel/cannonlake_rvp: Add Sleep states

Add sleep state to DSDT table.

Change-Id: Ic14e34e29d5f881949765dee5c6b433c1499c491
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/21976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
---
 src/mainboard/intel/cannonlake_rvp/dsdt.asl | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/mainboard/intel')

diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index 9f19cfb3ac..46d41e1656 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -39,4 +39,8 @@ DefinitionBlock(
 	// Chrome OS specific
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 	#endif
+
+	// Chipset specific sleep states
+	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
 }
-- 
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