From 9e61ca5674bf01950b4ab54ece3892a0937be379 Mon Sep 17 00:00:00 2001 From: Harsha B R Date: Sat, 4 Feb 2023 10:32:20 +0530 Subject: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN This patch enables PCIe port for WWAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module gets enumerated with cbmem -c. \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) Signed-off-by: Harsha B R Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/72777 Reviewed-by: Eric Lai Reviewed-by: Sridhar Siricilla Tested-by: build bot (Jenkins) --- .../intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 628a8cba01..1573cdffbb 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -79,6 +79,14 @@ chip soc/intel/meteorlake device ref tcss_xhci on end device ref tcss_dma0 on end device ref tcss_dma1 on end + device ref pcie_rp7 on + # Enable PCH PCIE RP 7 using CLK 1 + register "pcie_rp[PCIE_RP(7)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + end # WWAN device ref pcie_rp10 on # Enable SSD Gen4 PCIE 10 using CLK 8 register "pcie_rp[PCIE_RP(10)]" = "{ -- cgit v1.2.3