From 8b4677fbbf2dd9d748ecba023c4a07afcaa2d7d0 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 12 Jan 2024 16:22:19 +0100 Subject: soc/intel/elkhartlake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa Signed-off-by: Nico Huber Signed-off-by: Nicholas Sudsgaard Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921 Tested-by: build bot (Jenkins) Reviewed-by: Jan Samek Reviewed-by: Felix Singer --- src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 2c952bf9c1..732c39604d 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -42,14 +42,6 @@ chip soc/intel/elkhartlake register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" register "PcieClkSrcUsage[1]" = "0x06" register "PcieClkSrcUsage[2]" = "0x04" -- cgit v1.2.3