From 8256a9b715df14dc8914b641796344ac513cb889 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 29 Nov 2012 17:18:53 -0600 Subject: haswell: align pei_data structure with intel-framework The intel-framework code has an updated pei_data structure. Use the new structure and revision. Also, remove the scrambler seed saving in CMOS since that appears to be handled in the saved data from the reference code. Change-Id: Ie09a0a00646ab040e8ceff922048981d055d5cd2 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2630 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/intel/graysreef/cmos.layout | 4 ---- src/mainboard/intel/graysreef/romstage.c | 3 +-- 2 files changed, 1 insertion(+), 6 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/graysreef/cmos.layout b/src/mainboard/intel/graysreef/cmos.layout index afdd3c66ca..e8a088d583 100644 --- a/src/mainboard/intel/graysreef/cmos.layout +++ b/src/mainboard/intel/graysreef/cmos.layout @@ -92,10 +92,6 @@ entries 416 128 r 0 vbnv #544 440 r 0 unused -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c index 6e35d51bf8..da839f41c8 100644 --- a/src/mainboard/intel/graysreef/romstage.c +++ b/src/mainboard/intel/graysreef/romstage.c @@ -143,11 +143,10 @@ void main(unsigned long bist) rcba: DEFAULT_RCBA, pmbase: DEFAULT_PMBASE, gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, + temp_mmio_base: 0xfed08000, system_type: 0, // 0 Mobile, 1 Desktop/Server tseg_size: CONFIG_SMM_TSEG_SIZE, spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, ec_present: 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel -- cgit v1.2.3