From 7843bd560e65b0a83e99b42bdd58dd6363656c56 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:56:37 +0100 Subject: nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/intel/dg41wv/Makefile.inc | 3 +++ src/mainboard/intel/dg41wv/early_init.c | 48 +++++++++++++++++++++++++++++++++ src/mainboard/intel/dg41wv/romstage.c | 47 -------------------------------- src/mainboard/intel/dg43gt/Makefile.inc | 3 +++ src/mainboard/intel/dg43gt/early_init.c | 43 +++++++++++++++++++++++++++++ src/mainboard/intel/dg43gt/romstage.c | 42 ----------------------------- 6 files changed, 97 insertions(+), 89 deletions(-) create mode 100644 src/mainboard/intel/dg41wv/early_init.c delete mode 100644 src/mainboard/intel/dg41wv/romstage.c create mode 100644 src/mainboard/intel/dg43gt/early_init.c delete mode 100644 src/mainboard/intel/dg43gt/romstage.c (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/dg41wv/Makefile.inc b/src/mainboard/intel/dg41wv/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/intel/dg41wv/Makefile.inc +++ b/src/mainboard/intel/dg41wv/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg41wv/early_init.c b/src/mainboard/intel/dg41wv/early_init.c new file mode 100644 index 0000000000..3cb40955d0 --- /dev/null +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Set GPIOs on superio, enable UART */ + pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x2c, 0x13); + + pnp_exit_ext_func_mode(SERIAL_DEV); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D29IR) = 0x0237; +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c deleted file mode 100644 index ff018af5f6..0000000000 --- a/src/mainboard/intel/dg41wv/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) - -void mb_lpc_setup(void) -{ - /* Set GPIOs on superio, enable UART */ - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_set_logical_device(SERIAL_DEV); - - pnp_write_config(SERIAL_DEV, 0x2c, 0x13); - - pnp_exit_ext_func_mode(SERIAL_DEV); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* IRQ routing */ - RCBA16(D31IR) = 0x0132; - RCBA16(D29IR) = 0x0237; -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} diff --git a/src/mainboard/intel/dg43gt/Makefile.inc b/src/mainboard/intel/dg43gt/Makefile.inc index 6b3d94a037..f89d1302e3 100644 --- a/src/mainboard/intel/dg43gt/Makefile.inc +++ b/src/mainboard/intel/dg43gt/Makefile.inc @@ -14,4 +14,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg43gt/early_init.c b/src/mainboard/intel/dg43gt/early_init.c new file mode 100644 index 0000000000..8457707ba1 --- /dev/null +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) + +void bootblock_mainboard_early_init(void) +{ + RCBA32(0x3410) = 0x00060464; + RCBA32(RCBA_BUC) &= ~BUC_LAND; + RCBA32(0x3418) = 0x01320001; + RCBA32(0x341c) = 0xbf7f001f; + RCBA32(0x3430) = 0x00000002; + RCBA32(0x3f00) = 0x0000000b; + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c deleted file mode 100644 index 71fd87ad74..0000000000 --- a/src/mainboard/intel/dg43gt/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) - -void mb_lpc_setup(void) -{ - RCBA32(0x3410) = 0x00060464; - RCBA32(RCBA_BUC) &= ~BUC_LAND; - RCBA32(0x3418) = 0x01320001; - RCBA32(0x341c) = 0xbf7f001f; - RCBA32(0x3430) = 0x00000002; - RCBA32(0x3f00) = 0x0000000b; - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[1] = 0x51; - spd_map[2] = 0x52; - spd_map[3] = 0x53; -} -- cgit v1.2.3