From 698ee274c0cef8e1ef1ea6107f531973a4f97a20 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Mon, 9 Aug 2021 16:08:40 +0530 Subject: mb/intel/adlrvp: create dynamic power limits mechanism for thermal Add dynamic power limits selection mechanism for aldrvp board. BUG=None BRANCH=None TEST=Build FW and test on adlrvp with DPTF tool On adlrvp (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (55000, 55000) On adlrvp (682): Overriding DPTF power limits PL1 (5000, 45000) PL2 (115000, 115000) Change-Id: Id1aef0125c6e1e105665172f19bda271e232d94f Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/56880 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/Makefile.inc | 1 + .../intel/adlrvp/include/baseboard/variants.h | 13 +++++ src/mainboard/intel/adlrvp/mainboard.c | 7 +++ src/mainboard/intel/adlrvp/ramstage.c | 55 ++++++++++++++++++++++ 4 files changed, 76 insertions(+) create mode 100644 src/mainboard/intel/adlrvp/ramstage.c (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index ca9ba1445e..04c16455e8 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -24,6 +24,7 @@ ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += ramstage.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9a94db2c7a..bc2a57e98f 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -35,4 +35,17 @@ void variant_configure_early_gpio_pads(void); size_t variant_memory_sku(void); const struct mb_cfg *variant_memory_params(void); + +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); +struct cpu_power_limits { + uint16_t mchid; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; +}; +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index fd0a9bab8f..a113683e0e 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -28,6 +28,13 @@ static void mainboard_init(void *chip_info) if (CONFIG(EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); + + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ } #if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c new file mode 100644 index 0000000000..25a7c5b062 --- /dev/null +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +#include + +const struct cpu_power_limits limits[] = { + /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ + /* PL2 values are for performance configuration */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 55000, 55000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 64000, 64000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 115000, 115000 }, +}; + +void variant_update_power_limits(void) +{ + const struct device_path policy_path[] = { + { .type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_DPTF}, + { .type = DEVICE_PATH_GENERIC, .generic.id = 0} + }; + + const struct device *policy_dev = find_dev_nested_path(pci_root_bus(), + policy_path, ARRAY_SIZE(policy_path)); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { + if (mchid == limits[i].mchid) { + struct dptf_power_limits *settings = &config->controls.power_limits; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + printk(BIOS_INFO, "sumeet: Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power); + } + } +} + +void variant_devtree_update(void) +{ + variant_update_power_limits(); +} -- cgit v1.2.3