From 4e300cc780aada423b58af4aaeae457fa34ff741 Mon Sep 17 00:00:00 2001
From: John Zhao <john.zhao@intel.com>
Date: Wed, 22 Apr 2020 09:23:48 -0700
Subject: mb/intel/tigerlake: Include TCSS power management

Include TCSS RTD3 into ACPI DSDT table.

BUG=b:140290596
TEST=Booted to kernel and verified tcss xhci/pcierp/dma
power state D3 entry/exit.

Change-Id: I8cc5cfb572e15121059eb1fba41f931c59afbdf6
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/mainboard/intel/tglrvp/dsdt.asl | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mainboard/intel')

diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl
index af13d9f5c1..080072d4e0 100644
--- a/src/mainboard/intel/tglrvp/dsdt.asl
+++ b/src/mainboard/intel/tglrvp/dsdt.asl
@@ -27,6 +27,7 @@ DefinitionBlock(
 		{
 			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/tigerlake/acpi/southbridge.asl>
+			#include <soc/intel/tigerlake/acpi/tcss.asl>
 		}
 	}
 
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