From 4aa7d2d5ac7bc1e8f20cd36eb54af63d5b94c6c3 Mon Sep 17 00:00:00 2001 From: Harsha B R Date: Sat, 4 Feb 2023 11:09:24 +0530 Subject: mb/intel/mtlrvp: Enable WWAN ACPI This patch enables FM350GL 5G WWAN support for mtlrvp. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module 00:1c.6 is enumerated as part of lspci and cbmem -c in AP console. Also verify generation of PXSX Device as part of SSDT. Able to connect WiFi and access internet. cbmem -c: \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) SSDT: Scope (\_SB.PCI0.RP07) { Device (PXSX) Signed-off-by: Harsha B R Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/72779 Reviewed-by: Eric Lai Reviewed-by: Krishna P Bhat D Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla --- src/mainboard/intel/mtlrvp/Kconfig | 1 + .../mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 0d90a3b9bb..11a0daa9cc 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -28,6 +28,7 @@ config CHROMEOS config BOARD_SPECIFIC_OPTIONS def_bool y select INTEL_LPSS_UART_FOR_CONSOLE + select DRIVERS_WWAN_FM350GL config MAINBOARD_DIR default "intel/mtlrvp" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index ddb800262e..b6c5acac52 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -101,6 +101,23 @@ chip soc/intel/meteorlake .clk_req = 1, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp7_rtd3 on end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" + register "add_acpi_dma_property" = "true" + use rp7_rtd3 as rtd3dev + device generic 0 on end + end end # WWAN device ref pcie_rp8 on # Enable PCH PCIE RP 8 using CLK 5 -- cgit v1.2.3