From 4a91f6443121396b2339b06831249453055e3e24 Mon Sep 17 00:00:00 2001 From: York Yang Date: Tue, 25 Nov 2014 15:54:08 -0700 Subject: mainboard/intel/minnowmax: use Baytrail Gold3 FSP Baytrail Gold3 FSP support memory down configuration. Update Minnow Max to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use different FSP image. Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123 Signed-off-by: York Yang Reviewed-on: http://review.coreboot.org/7581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich Reviewed-by: Martin Roth --- src/mainboard/intel/minnowmax/Kconfig | 22 +++++----------------- src/mainboard/intel/minnowmax/devicetree.cb | 18 ++++++++++++++++++ src/mainboard/intel/minnowmax/romstage.c | 13 +++++++++++-- 3 files changed, 34 insertions(+), 19 deletions(-) mode change 100644 => 100755 src/mainboard/intel/minnowmax/Kconfig mode change 100644 => 100755 src/mainboard/intel/minnowmax/devicetree.cb mode change 100644 => 100755 src/mainboard/intel/minnowmax/romstage.c (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig old mode 100644 new mode 100755 index 229172c8fe..6a65382a17 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -57,10 +58,6 @@ config MINNOWMAX_2GB_SKU bool "2GB" endchoice -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config IRQ_SLOT_COUNT int default 18 @@ -73,23 +70,18 @@ config CACHE_ROM_SIZE_OVERRIDE hex default 0x800000 -config FSP_LOC - hex - default 0xfffc0000 - config FSP_FILE string - default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_2gb.bin" if MINNOWMAX_2GB_SKU - default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_1gb.bin" + default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" config MRC_CACHE_LOC_OVERRIDE hex - default 0xfff90000 + default 0xfff80000 depends on ENABLE_FSP_FAST_BOOT config CBFS_SIZE hex - default 0x00300000 + default 0x00200000 config DRIVERS_PS2_KEYBOARD bool @@ -119,10 +111,6 @@ config POST_DEVICE config VGA_BIOS bool - default n - -config VGA_BIOS_FILE - string - default "../intel/mainboard/intel/minnowmax/Vga.dat" if VGA_BIOS + default y if FSP_PACKAGE_DEFAULT endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb old mode 100644 new mode 100755 index dd999a09e0..ae11d6a020 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -36,6 +37,23 @@ chip soc/intel/fsp_baytrail register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "11" + register "DIMMtRPtRCD" = "11" + register "DIMMtWR" = "12" + register "DIMMtWTR" = "6" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "6" + register "DIMMtFAW" = "20" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c old mode 100644 new mode 100755 index 460c668a9a..af63cab4e9 --- a/src/mainboard/intel/minnowmax/romstage.c +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +21,7 @@ #include #include +#include "chip.h" /** * /brief mainboard call for setup that needs to be done before fsp init @@ -53,8 +55,15 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - /* Disable 2nd DIMM */ - UpdData->PcdMrcInitSPDAddr2 = 0x00; + /* + * Minnow Max Board : 1GB SKU uses 2Gb density memory + * 2GB SKU uses 4Gb densiry memory + * + * devicetree.cb assume 1GB SKU board + */ + if (CONFIG_MINNOWMAX_2GB_SKU) + UpdData->PcdMemoryParameters.DIMMDensity + += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT); return; } -- cgit v1.2.3