From 3fc42772bcc97fa6e5ff5235126ff30c359a5b7c Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Fri, 20 Nov 2015 11:47:40 +0530 Subject: intel/kunimitsu: Add VrConfig UPD parameters Cofigure VR settings for kunimitsu BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:311317 Change-Id: Ib2afe7694d2a807cea1befa73349bd21a3e7d909 Signed-off-by: Patrick Georgi Original-Commit-Id: c3548d7cb3a00826377e819f20d07167b4eb2c65 Original-Change-Id: I6b80f509bc0ab6f65f26eec0651a3b44fb38fbf9 Original-Signed-off-by: Barnali Sarkar Original-Signed-off-by: Rizwan Qureshi Original-Reviewed-on: https://chromium-review.googlesource.com/313068 Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/12945 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/intel/kunimitsu/devicetree.cb | 78 +++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ec67ce184e..adb89317b8 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -47,6 +47,84 @@ chip soc/intel/skylake # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled register "SerialIrqConfigSirqEnable" = "0x01" + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x1C, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0 \ + }" + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0, \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C ,\ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C, \ + .voltage_limit = 0x5F0 \ + }" + # Enable Root port 1 and 5. register "PcieRpEnable[0]" = "1" register "PcieRpEnable[4]" = "1" -- cgit v1.2.3