From 3af09bb16f19af2f455e592520cd7a3272391f9a Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 18 Aug 2020 22:32:47 -0700 Subject: mb/intel/tglrvp: Disable TBT_PCIE3 for UP4 Tiger Lake External Design Specification (Document #575683) states UP4 TBT_PCIE3 is not applicable. Disable TC3 for UP4. BUG=None Test=Built UP4 image successfully. Signed-off-by: John Zhao Change-Id: Icff8fccf9ac29c315c2a4dd08a3ec8a8efe9c453 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44572 Reviewed-by: Caveh Jalali Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ccc4df89bb..a79bf80073 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -153,7 +153,7 @@ chip soc/intel/tigerlake device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 on end # TBT_PCIe1 0x9A25 device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D -- cgit v1.2.3