From 3a873b5c9a70ec41488161b491ffe5ac94bb554e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 27 Nov 2020 00:20:18 +0530 Subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP TEST=Able to pass MRC training on DDR4/5 SKUs Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078 Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla Reviewed-by: V Sowmya Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index cab4ef93f3..5d374db2a6 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -12,7 +12,7 @@ static const struct mb_cfg ddr4_mem_config = { /* Baseboard Rcomp target values */ .rcomp_targets = {40, 30, 33, 33, 30}, - .dq_pins_interleaved = true, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ @@ -61,7 +61,7 @@ static const struct mb_cfg ddr5_mem_config = { /* Baseboard Rcomp target values */ .rcomp_targets = {50, 30, 30, 30, 27}, - .dq_pins_interleaved = true, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ -- cgit v1.2.3