From 332f14b60b241d1793401ea50b22785ad81c97cd Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Fri, 5 Sep 2014 16:29:41 +0200 Subject: bd82x6x: Move common bd82x6x S3 detect to bd82x6x code. Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281 Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/6921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/intel/emeraldlake2/romstage.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index c9c2b1d41f..220b1d731d 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -167,8 +167,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -250,24 +248,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ -- cgit v1.2.3