From 32d5d5b75799a139143afefe3822f926afb0c665 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 5 Apr 2023 17:40:38 +0530 Subject: mb/intel/mtlrvp: Use `-` over `.` in chromeos-debug-fsp.fmd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch renames debug FMD file (chromeos.debug-fsp.fmd) to chromeos-debug-fsp.fmd in order to match the file path name in `FMDFILE` config. TEST=Able to build intel/mtlrvp with this code change. Signed-off-by: Subrata Banik Change-Id: Ic8de07e4befa6b1ab8ab57d593c6939d87c48e9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74217 Tested-by: build bot (Jenkins) Reviewed-by: Usha P Reviewed-by: Dinesh Gehlot Reviewed-by: Eric Lai --- src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd | 48 +++++++++++++++++++++++ src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd | 48 ----------------------- 2 files changed, 48 insertions(+), 48 deletions(-) create mode 100644 src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd delete mode 100644 src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd new file mode 100644 index 0000000000..bd250f5fab --- /dev/null +++ b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd @@ -0,0 +1,48 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_ME + } + SI_BIOS 23M { + RW_SECTION_A 7604K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 4400K + } + RW_MISC 152K { + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7604K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 4400K + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd deleted file mode 100644 index bd250f5fab..0000000000 --- a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd +++ /dev/null @@ -1,48 +0,0 @@ -FLASH 32M { - SI_ALL 9M { - SI_DESC 16K - SI_ME - } - SI_BIOS 23M { - RW_SECTION_A 7604K { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 64 - ME_RW_A(CBFS) 4400K - } - RW_MISC 152K { - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - UNIFIED_MRC_CACHE(PRESERVE) 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - } - # This section starts at the 16M boundary in SPI flash. - # MTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7604K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - ME_RW_B(CBFS) 4400K - } - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO 8M { - RO_VPD(PRESERVE) 16K - RO_GSCVD 8K - RO_SECTION { - FMAP 2K - RO_FRID 64 - GBB@4K 12K - COREBOOT(CBFS) - } - } - } -} -- cgit v1.2.3