From 2f96970e1f4e586a4c5928fefab1bc0f98bc1351 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 20 Apr 2020 23:00:54 -0700 Subject: mb/intel/cedarisland_crb: Add dummy mainboard_memory_init_params() Add a dummy implementation (currently FSP defaults are meant for CRB). It is needed only to prevent build breakage. Change-Id: I67b1a693886a29bdaf23f1f3f249da52ba65451a Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40553 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/intel/cedarisland_crb/Makefile.inc | 1 + src/mainboard/intel/cedarisland_crb/romstage.c | 8 ++++++++ 2 files changed, 9 insertions(+) create mode 100644 src/mainboard/intel/cedarisland_crb/romstage.c (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/cedarisland_crb/Makefile.inc b/src/mainboard/intel/cedarisland_crb/Makefile.inc index 8501868fbf..9bd017393c 100644 --- a/src/mainboard/intel/cedarisland_crb/Makefile.inc +++ b/src/mainboard/intel/cedarisland_crb/Makefile.inc @@ -1 +1,2 @@ bootblock-y += bootblock.c +romstage-y += romstage.c diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c new file mode 100644 index 0000000000..94af1b6dfe --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ +} -- cgit v1.2.3