From 2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 3 Nov 2020 00:03:32 +0100 Subject: mb/**/cmos.layout: Remove crusty comments Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/intel/baskingridge/cmos.layout | 27 ---------------- src/mainboard/intel/d510mo/cmos.layout | 6 ---- src/mainboard/intel/d945gclf/cmos.layout | 26 --------------- src/mainboard/intel/dg41wv/cmos.layout | 25 --------------- src/mainboard/intel/dg43gt/cmos.layout | 24 -------------- src/mainboard/intel/emeraldlake2/cmos.layout | 28 ----------------- src/mainboard/intel/kblrvp/cmos.layout | 47 ---------------------------- src/mainboard/intel/kunimitsu/cmos.layout | 47 ---------------------------- src/mainboard/intel/saddlebrook/cmos.layout | 46 --------------------------- src/mainboard/intel/strago/cmos.layout | 47 ---------------------------- src/mainboard/intel/wtm2/cmos.layout | 27 ---------------- 11 files changed, 350 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index 7c4d614196..6d2caea110 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -3,58 +3,31 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index 0a329956af..fa9bd26736 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -3,22 +3,17 @@ # ----------------------------------------------------------------- entries - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -30,7 +25,6 @@ entries 416 512 s 0 boot_devices # coreboot config options: cpu -#945 7 r 0 unused # coreboot config options: northbridge 952 3 e 11 gfx_uma_size diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index e0d6ec5244..58f96f03f1 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -50,11 +26,9 @@ entries # coreboot config options: bootloader 416 512 s 0 boot_devices -#928 80 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index b1f6e77558..cbf83229c9 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -3,51 +3,26 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index 2174ecd097..0bd628c7a7 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -3,34 +3,13 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console @@ -42,12 +21,9 @@ entries 411 1 e 1 nmi # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 8c19c753b1..8d47ab18bc 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -3,50 +3,25 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -55,15 +30,12 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout index cc55ccfc71..82d91a3c76 100644 --- a/src/mainboard/intel/saddlebrook/cmos.layout +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -4,72 +4,26 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader -#544 440 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index da1b185c7e..3b2b829209 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -3,54 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -58,7 +32,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- -- cgit v1.2.3