From 133dcd386f2ae620b635446bb3d7b34d3b95eca8 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Fri, 10 Jul 2015 16:00:51 +0530 Subject: Kunimitsu: enable deep S5 This patche enables the deep S5 and disables Deep S3. Kunimitsu does not resume from deep S3. This change will unblock the S3 resume path on kunimitsu board. BRANCH=None BUG=chrome-os-partner:42331 TEST=Built and booted on kunimitsu; check s3 works. Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805 Original-Signed-off-by: Naveen Krishna Chatradhi Original-Reviewed-on: https://chromium-review.googlesource.com/291250 Original-Reviewed-by: Aaron Durbin Change-Id: I07b95a324a27ab658e80674686b47b86412ea097 Signed-off-by: Naveen Krishna Chatradhi Reviewed-on: http://review.coreboot.org/11274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/intel/kunimitsu/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 09e41b97da..b5f0dbb335 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -82,6 +82,13 @@ chip soc/intel/skylake # Integrated Sensor register "IshEnable" = "0" + # Enable deep Sx states + register "deep_s3_enable" = "0" + register "deep_s5_enable" = "1" + + # CPU Thermal participant device + register "Device4Enable" = "1" + # XDCI controller register "XdciEnable" = "0" @@ -131,6 +138,7 @@ chip soc/intel/skylake device pnp 0c09.0 on end end end # LPC Interface + device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech) device pci 1f.4 off end # SMBus Controller device pci 1f.5 on end # SPI -- cgit v1.2.3