From 0d4200fef396fb0d1fbf28b4ced475fbf59b5b85 Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Mon, 29 Apr 2019 10:18:24 -0700 Subject: soc/intel/cannonlake: Support different SPD read type for each slot Also clean up cannonlake_memcfg_init. The major changes include: (1) Add enum 'mem_info_read_type' to spd_info. (2) Add per-dimm-slot spd_info to cnl_mb_cfg. (3) Setup memory config for each slot independently. (4) Squash meminit_memcfg_spd(). BUG=chromium:960581, b:124990009 BRANCH=none TEST=boot hatch, hatch_whl, and kohaku Change-Id: I686a85996858204c20fd05ef24787a0487817c34 Signed-off-by: Philip Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513 Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/intel/coffeelake_rvp/memory.c | 25 +++++++++++++++++++++---- src/mainboard/intel/coffeelake_rvp/romstage.c | 10 +--------- 2 files changed, 22 insertions(+), 13 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index a13000cc13..b093a20d2c 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -20,6 +20,23 @@ #include static const struct cnl_mb_cfg baseboard_memcfg_cfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA0} + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA2} + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA4} + }, + .spd[3] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA6} + }, /* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. @@ -27,16 +44,16 @@ static const struct cnl_mb_cfg baseboard_memcfg_cfg = { * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 }, - .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* * Baseboard Rcomp target values. */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Baseboard is an interleaved design */ .dq_pins_interleaved = 1, diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index 1ab2d78b5a..09ef148e36 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -20,13 +20,5 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xA0, - .spd_smbus_address[1] = 0xA2, - .spd_smbus_address[2] = 0xA4, - .spd_smbus_address[3] = 0xA6, - }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memcfg_config(), &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); } -- cgit v1.2.3