From 07921540dda79d810d8bfc6be211513c238a0d63 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Fri, 17 Jun 2016 17:22:00 +0300
Subject: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
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Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
---
 src/mainboard/intel/d810e2cb/romstage.c | 4 ++--
 src/mainboard/intel/mtarvon/romstage.c  | 4 ++--
 src/mainboard/intel/truxton/romstage.c  | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/mainboard/intel')

diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
index 934cb173a1..5bcee0c544 100644
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ b/src/mainboard/intel/d810e2cb/romstage.c
@@ -23,14 +23,14 @@
 #include <southbridge/intel/i82801bx/i82801bx.h>
 #include <northbridge/intel/i82810/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <superio/smsc/smscsuperio/smscsuperio.h>
 #include "gpio.c"
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	/* Set southbridge and Super I/O GPIOs. */
 	mb_gpio_init();
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index b7d216e394..cb3e870043 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -28,6 +28,7 @@
 #include <superio/intel/i3100/i3100.h>
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
@@ -46,8 +47,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "arch/x86/lib/stages.c"
 #endif
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	msr_t msr;
 	u16 perf;
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 36f54953b9..4b64210c38 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -28,6 +28,7 @@
 #include <superio/intel/i3100/i3100.h>
 #include "lib/debug.c" // XXX
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
@@ -42,8 +43,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 
 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {
 		{
-- 
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