From bbbfd9d1906cb2d99385eae845a13a311f77ef78 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 3 Dec 2005 23:48:17 +0000 Subject: smaller fixups here and there, allowing some motherboards to compile or to fail later than before. dos2unix'ed the xe7501devkit files, that might have caused some problems before. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/intel/xe7501devkit/auto.c | 184 ++++++++++++++++---------------- 1 file changed, 92 insertions(+), 92 deletions(-) (limited to 'src/mainboard/intel/xe7501devkit/auto.c') diff --git a/src/mainboard/intel/xe7501devkit/auto.c b/src/mainboard/intel/xe7501devkit/auto.c index 8c635720af..1bd83a3187 100644 --- a/src/mainboard/intel/xe7501devkit/auto.c +++ b/src/mainboard/intel/xe7501devkit/auto.c @@ -1,92 +1,92 @@ -#define ASSEMBLY 1 - -#include -#include -#include -#include -#include -#include -#include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" -#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c" -#include "northbridge/intel/e7501/raminit.h" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/e7501/debug.c" -#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" - -#define SUPERIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1) - -static void hard_reset(void) -{ - outb(0x0e, 0x0cf9); -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7501/raminit.c" -#include "northbridge/intel/e7501/reset_test.c" -#include "sdram/generic_sdram.c" - - -// This function MUST appear last (ROMCC limitation) -static void main(unsigned long bist) -{ - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 }, - .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 }, - }, - }; - - if (bist == 0) - { - // Skip this if there was a built in self test failure - - early_mtrr_init(); - enable_lapic(); - } - - // Get the serial port running and print a welcome banner - - lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - // Halt if there was a built in self test failure - report_bist_failure(bist); - -// print_pci_devices(); - - // If this is a warm boot, some initialization can be skipped - - if (!bios_reset_detected()) - { - enable_smbus(); -// dump_spd_registers(&memctrl[0]); -// dump_smbus_registers(); - -// memreset_setup(); No-op for this chipset - sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); - } - - // NOTE: ROMCC dies with an internal compiler error - // if the following line is removed. - print_debug("SDRAM is up.\r\n"); -} +#define ASSEMBLY 1 + +#include +#include +#include +#include +#include +#include +#include +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c" +#include "northbridge/intel/e7501/raminit.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/e7501/debug.c" +#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" + +#define SUPERIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1) + +static void hard_reset(void) +{ + outb(0x0e, 0x0cf9); +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/e7501/raminit.c" +#include "northbridge/intel/e7501/reset_test.c" +#include "sdram/generic_sdram.c" + + +// This function MUST appear last (ROMCC limitation) +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .d0f1 = PCI_DEV(0, 0, 1), + .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 }, + .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 }, + }, + }; + + if (bist == 0) + { + // Skip this if there was a built in self test failure + + early_mtrr_init(); + enable_lapic(); + } + + // Get the serial port running and print a welcome banner + + lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + // Halt if there was a built in self test failure + report_bist_failure(bist); + +// print_pci_devices(); + + // If this is a warm boot, some initialization can be skipped + + if (!bios_reset_detected()) + { + enable_smbus(); +// dump_spd_registers(&memctrl[0]); +// dump_smbus_registers(); + +// memreset_setup(); No-op for this chipset + sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); + } + + // NOTE: ROMCC dies with an internal compiler error + // if the following line is removed. + print_debug("SDRAM is up.\r\n"); +} -- cgit v1.2.3