From 0aa06cbf18145eaf7ecd5a377f09e9d946aa36da Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 14 May 2014 17:03:15 -0700 Subject: wtm2: Convert to use soc/intel/broadwell Convert wtm2 board to use the broadwell soc chipset. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 with haswell and broadwell CQ-DEPEND=CL:201067 CQ-DEPEND=CL:*164226 Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/201070 Original-Reviewed-by: Aaron Durbin (cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866) Signed-off-by: Marc Jones Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda Reviewed-on: http://review.coreboot.org/8001 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/intel/wtm2/romstage.c | 129 +++++------------------------------- 1 file changed, 17 insertions(+), 112 deletions(-) (limited to 'src/mainboard/intel/wtm2/romstage.c') diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index b831244bd5..41bef93345 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -18,123 +18,28 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include -#include #include -#include "cpu/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include +#include +#include +#include +#include +#include #include "gpio.h" -const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQA - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)), - - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data pei_data; - RCBA_END_CONFIG, -}; + post_code(0x32); -void mainboard_romstage_entry(unsigned long bist) -{ - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, - .dmibar = DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa2, 0x00, 0xa2, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb2_ports = { - /* Length, Enable, OCn# */ - { 0x40, 1, USB_OC_PIN_SKIP, /* P0: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P1: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P2: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P3: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P4: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P5: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P6: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 0, USB_OC_PIN_SKIP, /* P7: */ - USB_PORT_FRONT_PANEL }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, USB_OC_PIN_SKIP }, /* P1; */ - { 1, USB_OC_PIN_SKIP }, /* P2; */ - { 1, USB_OC_PIN_SKIP }, /* P3; */ - { 1, USB_OC_PIN_SKIP }, /* P4; */ - }, - }; + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); - struct romstage_params romstage_params = { - .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], - .bist = bist, - .copy_spd = NULL, - }; + /* Fill out PEI DATA */ + memset(&pei_data, 0, sizeof(pei_data)); + mainboard_fill_pei_data(&pei_data); + rp->pei_data = &pei_data; - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); + romstage_common(rp); } -- cgit v1.2.3