From 467f31de92ca2ed9df1530270e9aabdd69fe8f88 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 8 Mar 2013 17:00:37 -0800 Subject: haswell/lynxpoint: Use new PCH/PM helper functions This makes use of the new functions from pmutil.c that take care of the differences between -H and -LP chipsets. It also adds support for the LynxPoint-LP GPE0 register block and the SMI/SCI routing differences. The FADT is updated to report the new 256 byte GPE0 block on wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address block so that part is zeroed to prevent IASL and the kernel from complaining about a mismatch. This was tested on WTM2. Unfortunately I am still unable to get an SCI delivered from the EC but I suspect that is due to a magic command needed to put the EC in ACPI mode. Instead I verified that all of the power management and GPIO registers were set to expected values. I also tested transitions into S3 and S5 from both the kernel and by pressing the power button at the developer mode screen and they all function as expected. Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/2816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/intel/wtm2/devicetree.cb | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src/mainboard/intel/wtm2/devicetree.cb') diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index db7c9988c7..80c86273d8 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -41,12 +41,11 @@ chip northbridge/intel/haswell register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" - register "gpe0_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" -- cgit v1.2.3