From afad056c2298824caeb2c58d1541576c73bfef5d Mon Sep 17 00:00:00 2001
From: Duncan Laurie <dlaurie@chromium.org>
Date: Mon, 14 Jan 2013 08:50:03 -0800
Subject: Add Intel Whitetip Mountain 2 mainboard

This is mostly a copy of Whitetip Mountain 1 with specific GPIO
map for this Customer Reference Board (CRB).

This mainboard currently has basic funcionality and is able to
boot a Linux Kernel but many of the new Haswell ULT specific
devices are not yet enabled.

Change-Id: I999452d86f00a2c245fa39b1b76080f6a3b1e352
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2725
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 src/mainboard/intel/wtm2/chromeos.c | 77 +++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 src/mainboard/intel/wtm2/chromeos.c

(limited to 'src/mainboard/intel/wtm2/chromeos.c')

diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
new file mode 100644
index 0000000000..1864754e88
--- /dev/null
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+#include <southbridge/intel/lynxpoint/pch.h>
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT	6
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+static void fill_lb_gpio(struct lb_gpio *gpio, int num,
+			 int polarity, const char *name, int force)
+{
+	memset(gpio, 0, sizeof(*gpio));
+	gpio->port = num;
+	gpio->polarity = polarity;
+	if (force >= 0)
+		gpio->value = force;
+	else if (num >= 0)
+		gpio->value = get_gpio(num);
+	strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio *gpio;
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	gpio = gpios->gpios;
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", 0); // force off
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", 1); // force on
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded);
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+	return 1; // force on
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0; // force off
+}
-- 
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