From ecc459301f54d412bba67507e7e9fbac1834f0c2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 24 Aug 2021 13:47:00 -0700 Subject: mb/intel/tglrvp: Enable USB4 resources using SoC Kconfig This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` Kconfig to enable USB4 resources and drops the configuration in mainboard. Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/tglrvp/Kconfig | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'src/mainboard/intel/tglrvp') diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 117343596e..2c4c48a438 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_CSE_LITE_SKU select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_SPI_TPM_CR50 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SPI_TPM config CHROMEOS @@ -53,21 +54,6 @@ config MAINBOARD_FAMILY string default "Intel_tglrvp" -config PCIEXP_HOTPLUG - default y - -config PCIEXP_HOTPLUG_BUSES - int - default 42 - -config PCIEXP_HOTPLUG_MEM - hex - default 0xc200000 # 194 MiB - -config PCIEXP_HOTPLUG_PREFETCH_MEM - hex - default 0x1c00000 # 448 MiB - config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -- cgit v1.2.3