From 03b20350e39c46b141a2f033332b459ab2d4e3d6 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 24 Jan 2020 17:31:51 -0800 Subject: mb/intel/tglrvp: pin mux for image clocks pin mux for IMGCLKOUT_0 and IMGCLKOUT_1 BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux for Image clocks pins(GPP_D4, GPP_H20) Signed-off-by: Wonkyu Kim Change-Id: Ifb0c2b17dd481ef6c19bdf9ee84f47ef08d7b9a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38563 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/intel/tglrvp') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 69bb931611..d1dc4ca251 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -28,6 +28,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_R6, 0, PLTRST), PAD_CFG_GPO(GPP_H12, 0, PLTRST), + + /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), }; /* Early pad configuration in bootblock */ -- cgit v1.2.3