From 5b1f335ef8aed95e01f040bc7074fb00acc8ab7e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 26 Mar 2020 15:36:19 -0700 Subject: soc/intel/tigerlake: Reorganize memory initialization support This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added. 1. It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. 2. spd_info structure is organized to allow mixed topologies as well. 3. DQ/DQS maps are organized to reflect hardware configuration. TEST=Verified that volteer still boots and memory initialization is successful. Signed-off-by: Furquan Shaikh Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- .../baseboard/include/baseboard/variants.h | 2 +- .../intel/tglrvp/variants/tglrvp_up3/memory.c | 63 ++++++++++++++-------- .../intel/tglrvp/variants/tglrvp_up4/memory.c | 63 ++++++++++++++-------- 3 files changed, 85 insertions(+), 43 deletions(-) (limited to 'src/mainboard/intel/tglrvp/variants') diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index b7b69f29fd..b38daff853 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -28,6 +28,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); size_t variant_memory_sku(void); -const struct mb_lpddr4x_cfg *variant_memory_params(void); +const struct lpddr4x_cfg *variant_memory_params(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index 1cb0df52df..ad2f24f9c1 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -21,38 +21,59 @@ size_t __weak variant_memory_sku(void) return 0; } -static const struct mb_lpddr4x_cfg mem_config = { +static const struct lpddr4x_cfg mem_config = { /* DQ byte map */ .dq_map = { - { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ - 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ - { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ - 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ - { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ - 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ - { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ - 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ - { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ - 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ - { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ - 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ - { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ - 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ - { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ - 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + [0] = { + { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */ + { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */ + }, + [1] = { + { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */ + { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */ + { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */ + { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */ + { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */ + { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */ + { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */ + { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, - { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ }, .ect = 1, /* Early Command Training */ }; -const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +const struct lpddr4x_cfg *__weak variant_memory_params(void) { return &mem_config; } diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index 651550c753..929d0cca89 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -21,38 +21,59 @@ size_t __weak variant_memory_sku(void) return 0; } -static const struct mb_lpddr4x_cfg mem_config = { +static const struct lpddr4x_cfg mem_config = { /* DQ byte map */ .dq_map = { - { 8, 9, 12, 11, 13, 15, 10, 14, /* Byte 0 */ - 4, 6, 0, 2, 5, 7, 1, 3 }, /* Byte 1 */ - { 2, 3, 0, 6, 1, 7, 5, 4, /* Byte 2 */ - 15, 14, 13, 8, 12, 11, 9, 10 }, /* Byte 3 */ - { 1, 0, 3, 2, 5, 4, 7, 6, /* Byte 4 */ - 14, 15, 12, 13, 8, 10, 9, 11 }, /* Byte 5 */ - { 8, 10, 11, 9, 15, 12, 14, 13, /* Byte 6 */ - 4, 7, 6, 5, 2, 0, 1, 3 }, /* Byte 7 */ - { 8, 9, 10, 11, 13, 12, 15, 14, /* Byte 0 */ - 7, 6, 4, 5, 0, 2, 1, 3 }, /* Byte 1 */ - { 1, 3, 0, 2, 6, 4, 5, 7, /* Byte 2 */ - 14, 15, 10, 12, 8, 13, 11, 9 }, /* Byte 3 */ - { 1, 0, 2, 4, 5, 3, 7, 6, /* Byte 4 */ - 12, 14, 15, 13, 9, 10, 8, 11 }, /* Byte 5 */ - { 11, 9, 8, 13, 12, 14, 15, 10, /* Byte 6 */ - 4, 7, 5, 1, 2, 6, 3, 0 } /* Byte 7 */ + [0] = { + { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, - { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ }, .ect = 1, /* Early Command Training */ }; -const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +const struct lpddr4x_cfg *__weak variant_memory_params(void) { return &mem_config; } -- cgit v1.2.3